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| HT95R54/ht95r55 cid phone 8-bit mcu rev. 1.00 1 march 3, 2010 general description the series of cid phone mcu are 8-bit high perfor - mance, risc architecture microcontroller devices spe - cially designed for telephone applications. devices flexibility are enhanced with their internal special fea - tures such as power-down and wake-up functions, dtmf generator, dtmf receiver, fsk decoder, pfd driver, spi and i 2 c interface, audio dac output, etc. these features combine to ensure applications require a minimum of external components and therefore re - duce overall product costs. having the advantages of low-power consumption, high-performance, i/o flexibility as well as low-cost, these devices have the versatility to suit a wide range of application possibilities such as fsk & dtmf mode caller id phone, home security products, deluxe fea - ture phones, cordless phones, fax and answering ma - chines, etc. the device will be ideally suited for phone products that comply with versatile dialer specification requirements for different areas or countries. the device is fully sup - ported by the holtek range of fully functional develop - ment and programming tools, providing a means for fast and efficient product development cycles. features operating voltage: f sys =3.58mhz: 2.2v~5.5v f sys =7.16mhz: 3.0v~5.5v f sys =10.74mhz: 3.0v~5.5v f sys =14.32mhz: 4.5v~5.5v program memory: 8k 16 (HT95R54) 16k 16 (ht95r55) 2112 8 data memory 38 bidirectional i/os with pull-high options 2 nmos output-only lines external interrupt input three 16-bit timers with interrupts timer external input 8-level stack 32768hz system oscillator 32768hz up to 14.32mhz frequency-up circuit real time clock function watchdog timer function pfd driver output serial interfaces module: sim for spi or i 2 c internal dtmf generator internal dtmf receiver internal fsk decoder support bell 202 and v.23 support ring and line reverse detection 12-bit audio dac output power-down and wake-up feature for power-saving operation: idle mode, sleep mode, green mode and normal mode up to 0.28 s instruction cycle with 14.32mhz system clock at v dd =4.5v~5.5v bit manipulation instructions table read function 63 powerful instructions all instructions executed in 1 or 2 machine cycles low voltage reset function supported by comprehensive suite of hardware and software tools internal low battery detector software controlled r-type lcd driver (scom) 64-pin lqfp package technical document application note ha0075e mcu reset and oscillator circuits application note
selection table part no. program memory data memory i/o timer external interrupt r-type lcd i 2 c/ spi d/a dtmf generator/ receiver fsk decoder stack package HT95R54 8k 16 2112 8 40 16-bit 3 4 4com 12-bit1 8 64lqfp ht95r55 16k 16 2112 8 40 16-bit 3 4 4com 12-bit1 8 64lqfp note: these devices are only available in otp versions. block diagram pin assignment HT95R54/ht95r55 rev. 1.00 2 march 3, 2010 ! ! " ! ! # # $ ! % & ' ( ) * ! + + , # - ( . / 0 & ! 1 ! ! / 2 + 3 4 - & % 5 6 ( ' 7 - 8 - - - & - % & 8 & - & & & % & 5 & 6 & ( & ' & ( 8( -( &( %( 5 & 7 % 8 % - % & 6 &6 %6 56 66 (6 '6 6 7 - 5 - 6 - ( 5 % 5 5 5 6 5 ( 5 ' 5 % ( % ' % % 7 5 8 5 - 5 & % % % 5 % 6 - ' - - 7 5 76 86 - 1 ' . 9 : & : & : : ; : 9 : % ; 9 9 : % 8 < ! 9 ' 9 ( 9 6 . ; 9 5 . ! + 2 . : 9 % . ! 9 & . ! 2 . ! + 9 - . . 1 9 8 . ' ( 6 5 % & - 9 ! 8 ! - . 1 " ! & ! % ! 5 . 8 ! 6 ! ( . - ! ' 1 8 1 - 1 & 1 % 1 5 1 6 1 ( + 4 ; : : < - < & ; ' ( 6 5 % . ! % & . ! & - . ! - 8 . ! 8 pin description pad name i/o options description pa0~pa7 i/o pull-high wake-up bidirectional 8-bit input/output port. each individual pin on this port can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. pc0, pc5, pc7 i/o pull-high bidirectional input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. when the multi-function interrupt is enabled an interrupt will be generated whenever pc0 or pc5 has a falling edge, or pc7 has a rising edge. when in the idle mode such an interrupt will wake up the device. pc1/aud pc4/tmr0 pc6/tmr1 i/o dac output pull-high bidirectional input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. pc1 is also d/a pin for audio output for driving an external transistor or power amplifier. pin pc4 and pc6 are pin-shared with the external timer input pin tmr0 and tmr1 respectively. pc2, pc3 o nmos output structures pd0/scom0 pd1/scom1 pd2/scom2 pd3/scom3 pd4~pd7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which nibble on the port have pull-high resistors. pd0~pd3 also support lcd software com port function. pe0/sdo pe1/sdi/sda pe2/sck/scl pe3/scs pe4/pclk/vddio pe5/pint pe6~pe7 i/o pull-high schmitt trigger input and cmos output. i 2 c and spi functional pins: sdo, sdi/sda, sck/scl, scs , pclk, pint are pin-shared with pe0~ pe5 re- spectively. for i 2 c, pe2 and pe1 used as scl and sda of i 2 c respectively. for use as spi, pe0~pe3 used as sdo, sdi, sck, scs of spi respectively. sdo is a serial interface data output. sck is a serial interface clock input/out- put (initial is input). scs is a chip select pin of the serial peripheral interface, input for slave mode and output for master mode. sdi is a serial interface data input. pclk is a peripheral clock. pint is external peripheral interrupt pin. once the spi/i 2 c bus function is used, the pe0~pe3 could not be used as normal i/o pins. pe4/pclk is pin shared with vddio which is selected by configuration option. pe4 i/o function & pclk output function will be disabled when this pin used as vddio. vddio is used to provide the spi/i 2 c interface i/os a pull high voltage, set by external power supplier, other than the device operating voltage. the purpose of this design is to cope with the voltage differ - ence between master device and slave device, such as voice flash memory. pf0~pf7 i/o pull-high bidirectional 8-bit input/output port.software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which nibble on the port have pull-high resistors. int i external interrupt schmitt trigger input. edge trigger activated on high to low transition. no pull-high resistor. dtmf o dual tone multi frequency output pfd o cmos output structure programmable frequency divider pin lbin i this pin detects low battery conditions using an external resistor network to define the low battery threshold voltage. rt/gt i/o tone acquisition time and release time can be set through connection with ex - ternal resistor and capacitor cmos in/out for dtmf receiver, est o early steering output cmos out for dtmf receiver. vp i operational amplifier non-inverting input for dtmf receiver. vn i operational amplifier inverting input for dtmf receiver. gs o operational amplifier output terminal for dtmf receiver. HT95R54/ht95r55 rev. 1.00 3 march 3, 2010 pad name i/o options description vref o reference voltage output, normally v dd / 2 for dtmf receiver. tip i input pin connected to the tip side of the twisted pair wires for fsk decoder. it is internally biased to 1 / 2 vdd when the device is in power-up mode. this pin must be dc isolated from the line. ring i input pin connected to the ring side of the twisted pair wires for fsk decoder. it is internally biased to 1 / 2 vdd when the device is in power-up mode. this pin must be dc isolated from the line. rdet, lbin i this pin detects ring energy on the line through an attenuating network for fsk decoder. rtimeb schmitt trigger input and nmos output pin which functions with rdet1 pin to make an rc network that performs ring detection function for fsk decoder. x1 x2 i o x1 and x2 are connected to an external 32768hz crystal or resonator for the system clock. xc external low pass filter pin used for the frequency up conversion circuit. res i schmitt trigger reset input. active low. vdd positive power supply vss negative power supply, ground. vdd2 dtmf receiver positive power supply vss2 dtmf receiver negative power supply vdd3 positive power supply for fsk decoder vss3 negative power supply for fsk decoder note: each pin on pa can be programmed through a configuration option to have a wake-up function. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT95R54/ht95r55 rev. 1.00 4 march 3, 2010 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions general v dd operating voltage 2.2 5.5 v cpu i idl1 idle mode current 1 3v 32768hz and 3.58mhz oscillator off, system halt, wdt off, no load 1.5 a 5v 2 i idl2 idle mode current 2 3v 32768hz and 3.58mhz oscillator off, system halt, wdt on, no load 5 a 5v 10 i slp sleep mode current 3v 32768hz on, 3.58mhz oscillator off, system halt, no load 15 a 5v 30 i grn green mode current 3v 32768hz on, 3.58mhz oscilla - tor off, system on, no load 25 a 5v 50 i nor1 normal mode current 1 3v 32768hz on, 3.58mhz oscillator on, system on, dtmf generator off, receiver off, fsk decoder off, no load 2 ma 5v 3 i nor2 normal mode current 2 3v 32768hz on, 3.58mhz oscillator on, system on, dtmf generator on, receiver on, fsk decoder on, no load 4 ma 5v 6 r ph pull-high resistor 3v 66 200 330 k 5v 33 100 166 v il1 input low voltage for i/o and int 0 0.3v dd v v ih1 input high voltage for i/o and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol1 i/o port sink current 3v v ol = 0.1v dd 34 ma 5v 4 6 i ol2 pc2, pc3 sink current 5v pc2/pc3= 0.5v 2.5 ma i oh1 i/o port source current 3v v oh = 0.9v dd 1 2 ma 5v 2 3 i oh2 pc2, pc3 leakage current 5v pc2/pc3= 5v 2.5 a v lbin low battery detection reference voltage 5v 1.05 1.15 1.25 v i scom scom operating current 5v scomc, isel[1:0]=00 17.5 25.0 32.5 a scomc, isel[1:0]=01 35 50 65 a scomc, isel[1:0]=10 70 100 130 a scomc, isel[1:0]=11 140 200 260 a v scom v dd /2 voltage for lcd com 5v no load 0.475 0.500 0.525 v dd HT95R54/ht95r55 rev. 1.00 5 march 3, 2010 symbol parameter test conditions min. typ. max. unit v dd conditions dtmf generator (operating temperature: 20 cto85 c v tdc dtmf output dc level 0.45v dd 0.7v dd v v tol dtmf sink current v dtmf = 0.5v 0.1 ma dtmf receiver r in input impedance (vp, vn) 5v 10 m i ol3 sink current (est) 5v v out = 0.5v 1 2.5 ma i oh3 source current (est) 5v v out = 4.5v 0.4 0.8 ma low-voltage reset v lvr1 low voltage reset 1 (note 2) configuration option= 4.2v 3.98 4.2 4.42 v v lvr2 low voltage reset 2 (note 2) configuration option= 3.15v 2.98 3.15 3.32 v v lvr3 low voltage reset 3 (note 2) configuration option= 2.1v 1.98 2.1 2.22 v note: 1. distortion: t.h.d.=20 log 2. vi, vh: row group and column group signals 3. v1, v2, ....., vn: harmonic signals (bw=300hz~3500hz) a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions general f sys1 system clock 1 normal mode 32768hz crystal oscillator 3.5795 mhz normal mode, x2 pll 7.16 mhz normal mode, x3 pll 10.74 mhz normal mode, x4 pll 14.32 mhz f sys2 system clock 2 green mode, 32768hz crystal oscillator 32 khz t sst system start-up timer period power-up, reset or wake-up from halt 1024 t sys t lvr low voltage width to reset 1 ms t wake wake-up time for 32768hz crystal osc 3v 32khz oscillator off on 200 ms t fup settling time for 32768hz to hclk: pll (frequency up conversion) 3v 32khz oscillator is on; hclk oscillator off on 20 ms t s2g time from sleep mode to green mode wake-up from sleep mode 0 ms HT95R54/ht95r55 rev. 1.00 6 march 3, 2010 == & - & & & = & = & symbol parameter test conditions min. typ. max. unit v dd conditions mcu t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 t res external reset low pulse width 1 s t int interrupt pulse width 1 s dtmf generator (operating temperature: 20 cto85 c f dtmfo single tone output frequency 2.5v microcontroller normal mode; dtmf generator single tone test mode 690 704 hz 762 778 843 861 932 950 1197 1221 1323 1349 1462 1492 1617 1649 v tac dtmf output ac level row group, r l =5k 120 155 180 mv rms r l dtmf output load t.h.d. 23db 5 k a cr column pre-emphasis row group= 0db 1 2 3 db thd tone signal distortion r l =5k 30 23 db dtmf receiver signal (f sys = 3.5795mhz) input signal level 3v 36 6 dbm 5v 29 1 twisted accept limit (positive) 5v 10 db twisted accept limit (negative) 5v 10 db dial tone tolerance 5v 18 db noise tolerance 5v 12 db third tone tolerance 5v 16 db frequency deviation acceptance 5v 1.5 % frequency deviation rejection 5v 3.5 % t pu power-up time 5v 30 ms HT95R54/ht95r55 rev. 1.00 7 march 3, 2010 symbol parameter test conditions min. typ. max. unit v dd conditions dtmf receiver gain setting amplifier (f sys = 3.5795mhz) r in input resistance 5v 10 m i in input leakage current 5v vss<(wp, wn) 4.5 v pp r l load resistance (gs) 5v 50 k c l load capacitance (gs) 5v 100 pf v cm common mode range 5v no load 3 v pp dtmf receiver steering control (f sys = 3.5795mhz) t dp tone present detection time 5v 51114ms t da tone absent detection time 5v 4 8.5 ms t acc acceptable tone duration 5v 42 ms t rej rejected tone duration 5v 20 ms t ia acceptable inter-digit pause 5v 42 ms t ir rejected inter-digit pause 5v 20 ms fsk decoder input sensitivity: tip, ring 40 45 dbm transmission rate 5v 1188 1200 1212 baud s/n signal to noise ratio 20 db band-pass filter frequency response relative to 1700hz at 0dbm 60hz 550hz 2700hz 3300hz 64 4 3 34 db carrier detect sensitivity 48 dbm t supd power up to fsk signal set up time 15 ms HT95R54/ht95r55 rev. 1.00 8 march 3, 2010 power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 0mv rr vdd vdd raising rate to ensure power-on reset 0.05 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 200 ms HT95R54/ht95r55 rev. 1.00 9 march 3, 2010 : : : HT95R54/ht95r55 rev. 1.00 10 march 3, 2010 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. this makes these devices suitable for low-cost, high-volume production for phone controller applications requiring up to 16k words of program memory and 2112 bytes of data memory storage. clocking and pipelining the system clock is derived from an external 32768hz crystal/resonator which then generates a high fre - quency on system clock using internal frequency-up converter circuitry. this internal clock is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the be - ginning of the t1 clock during which time a new instruc - tion is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef - fectively executed in one instruction cycle. the excep - tion to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. > ? ! @ 9 a # > ? ! - @ > ? ! = - @ 9 a # > ? ! @ > ? ! = & @ 9 a # > ? ! = - @ ! ! = - ! = & ! ? ! @ ! - ! # ! & ! % ! 5 $ system clocking and pipelining > - 9 a # > - > & # $ - & % 5 6 ( 9 + 1 b c : 1 d e - & ) f ! 1 + + 9 + 1 b ! + e - & ) f c c ; 9 a # > & > % > ( 9 a # > ( > ' instruction fetching HT95R54/ht95r55 rev. 1.00 11 march 3, 2010 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low regis - ter, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 8 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer, sp, which can also neither be read from nor written to. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. mode program counter bits b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 00000000000000 external interrupt 00000000000100 timer/event counter 0 overflow 00000000001000 timer/event counter 1 overflow 00000000001100 peripheral interrupt 00000000010000 rtc interrupt 00000000010100 multi-function interrupt 00000000011000 skip program counter + 2 (within current bank) loading pcl pc13 pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc13~pc8: current program counter bits @7~@0: pcl bits #12~#0: instruction code address bits s13~s0: stack register bits for the HT95R54, the table address location is 13 bits,i.e. from b12~b0. for the ht95r55, the table address location is 14 bits,i.e. from b13~b0. for the HT95R54, the bp5 bit is fixed at 0 . - % - & ' 8 4 > 6 HT95R54/ht95r55 rev. 1.00 12 march 3, 2010 arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. for these devices the pro - gram memory is an otp type, which means it can be programmed once. device capacity HT95R54 8k16 ht95r55 16k16 structure the program memory has a capacity of 8k 16 to 16k 16. the program memory is addressed by the pro - gram counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the external interrupt. if the ex- ternal interrupt pin on the device goes low, the program will jump to this location and begin execution if the ex- ternal interrupt is enabled and the stack is not full. location 008h this internal vector is used by the timer/event coun- ter 0. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter 0 interrupt is enabled and the stack is not full. location 00ch this internal vector is used by the timer/event counter 1. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter 1 interrupt is enabled and the stack is not full. location 010h this internal vector is used by the dtmf receiver and fsk decoder. when the dtmf receiver and fsk de - coder are enabled, if the dtmf receiver detects a valid character available or ring/line reversal is de - tected or fsk carrier is detected or fsk packet data is ready or fsk raw data has a falling edge, the program will jump to this location and begin execution if the pe - ripheral interrupt is enabled and the stack is not full. location 014h this location is used by the rtc. when the rtc is en - abled and a time-out occurs, the program will jump to this location and begin execution if the rtc interrupt is enabled and the stack is not full. ! # + / - + / & + / 8 8 ) 9 a # $ 8 # $ ! # $ 9 a # $ 8 # $ - # $ # g # # $ - # $ 8 5 ) 8 ) 8 ! ) - 8 ) - 5 ) - ) - ) % ) - 6 - ( $ # $ # g # # $ ! # $ $ # $ program memory structure HT95R54/ht95r55 rev. 1.00 13 march 3, 2010 location 018h this location is used by the multi-function interrupt. if a falling edge transition is detected on pc0 or pc5, or a rising edge transition is detected on pc7 or an spi/i2c interrupt occurs, or an external peripheral fall - ing edge transition, or a timer 2 overflow, the program will jump to this location and begin execution if the multi-function interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will have uncertain values. the following diagram illustrates the addressing/data flow of the look-up table: table program example the following example shows how the table pointer and table data is defined and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 3f00h which refers to the start address of the last page within the 16k pro - gram memory of the microcontroller. the table pointer is setup here to have an initial value of 06h . this will en - sure that the first data read from the data table will be at the program memory address 3f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is exe - cuted. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter- rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. ! # ) 4 4 + 4 + ) $ g e f ) 4 g ! + 3 4 g ! look-up table instruction table location bits b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc13 pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 111111@7@6@5@4@3@2@1@0 table location note: for the HT95R54, the table address location is 13 bits,i.e. from b12~b0. for the ht95r55, the table address location is 14 bits,i.e. from b13~b0. pc13~pc8: current program counter bits @7~@0: table pointer lower-order bits (tblp) HT95R54/ht95r55 rev. 1.00 14 march 3, 2010 data memory the data memory is a volatile area of 8-bit wide ram in- ternal memory and is the location where temporary in- formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di- rectly under program control, however, some remain protected from user manipulation. the second area of ram data memory is reserved for general purpose use. all locations within this area are read and write accessi - ble under program control. structure the special purpose and general purpose data mem- ory are located at consecutive locations. all are imple- mented in ram and are 8 bits wide. the start address of the data memory is the address 00h. registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. note that af- ter power-on, the contents of the data memory, will be in an unknown condition, the programmer must therefore ensure that the data memory is properly initialised. the special purpose data memory is located in bank 0 while the general purpose data memory is divided into 11 individual areas or banks known as bank 0 to bank 10. switching between different banks is achieved by setting the bank pointer to the correct value. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 3f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 3f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 0fh will be transferred to the high byte ; register tblh : : org 3f00h ; sets initial address of the last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : 4 - 8 8 8 ) 5 8 ) ) % ) 4 % 4 & 4 - 4 8 $ # $ 4 8 # $ 4 - h - 8 # $ data memory structure HT95R54/ht95r55 rev. 1.00 15 march 3, 2010 general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. as the general purpose data memory is located within 11 different banks, it is first necessary to ensure that the bank pointer is properly set to the cor - rect value before accessing the general purpose data memory. only bank 0 data can be read directly. indirect addressing of bank 0 is executed using indirect ad - dressing register iar0 and memory pointer mp0. data in banks 1~10 can only be read indirectly using indirect addressing register iar1 and memory pointer mp1. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant spe- cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . although the special pur- pose data memory registers are located in bank 0, they will still be accessible even if the bank pointer has se- lected banks 1~10. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the ram data memory area. these registers ensure correct op - eration of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as i/o data control. the location of these registers within the ram data memory begins at the address 00h . any unused data memory locations between these special function registers and the point where the general pur - pose memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00h . indirect addressing register iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in 1 8 8 1 - - 4 1 ! ! ! + 4 + 4 + ) 1 " ; ! 8 8 ) 8 + 8 ! - ) - + - ! 1 1 ! ! ! ! ! 9 9 ! ; ! - ! < ! < ! ! 9 i - 9 ! + 8 ! + - 1 . ! + & ! ! ! 8 ! - ! : ! 9 ! 1 + 1 ) : + ! & ) & + & ! 2 ! 2 2 + 4 ! 9 ! 8 8 ) 8 - ) 8 & ) 8 % ) 8 5 ) 8 6 ) 8 ( ) 8 ' ) 8 ) 8 7 ) 8 1 ) 8 4 ) 8 ! ) 8 ) 8 9 ) 8 ) - 8 ) - - ) - & ) - % ) - 5 ) - 6 ) - ( ) - ' ) - ) - 7 ) - 1 ) - 4 ) - ! ) - ) - 9 ) - ) & 8 ) & - ) & & ) & % ) & 5 ) & 6 ) & ( ) & ' ) & ) & 7 ) & 1 ) & 4 ) & ! ) & ) & 9 ) & ) % 8 ) % - ) % & ) % % ) % 5 ) % 6 ) % ( ) % ' ) % ) % 7 ) % 1 ) % 4 ) % ! ) % ) % 9 ) % ) 5 8 ) c " # d j 8 8 j ) special purpose data memory structure HT95R54/ht95r55 rev. 1.00 16 march 3, 2010 no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can ac - cess data from both bank 0 and bank 1. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointer mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers pro - viding a convenient way with which to address and track data. when any operation to the relevant indirect ad - dressing registers is carried out, the actual address that the microcontroller is directed to, is the address speci - fied by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0 only, while mp1 and iar1 are used to access data from banks 1~10. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. bank pointer bp the data memory ram is divided into eleven banks, known as bank 0~bank 10. all of the special purpose registers are contained in bank 0. selecting the required data memory area is achieved using the bank pointer. if data in bank 0 is to be accessed, then the bp register must be loaded with the value 00 , while if data in bank 1 is to be accessed, then the bp register must be loaded with the value 01 and so on for the other registers. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irrespective of the value of the bank pointer. 4 % d 4 & d 4 - d 4 8 8 - & % 5 6 ( ' 7 - 8 - - h - 6 ; $ d j 8 j 2 ? ; c g a j 8 j g ) 7 6 6 5 @ ; $ d j 8 j ' 8 4 8 4 8 4 - 4 & 4 % 4 5 4 6 4 ( 4 ' 4 4 7 4 - 8 ; $ 4 -4 &4 % 4 6 bank pointer HT95R54/ht95r55 rev. 1.00 17 march 3, 2010 the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from bank 0 to bank 10. directly addressing the data memory will always result in bank 0 being ac - cessed irrespective of the value of the bank pointer. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro- grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple- mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo- cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the pro - gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage- ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. : k 1 ! ! ! " # $ # % & ' ! ! g 1 # a g k g / g 3 g ( ! ) ' ! 3 3 g # g ; $ d j 8 j ' 8 status register HT95R54/ht95r55 rev. 1.00 18 march 3, 2010 the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control register intc0, intc1 these two 8-bit register, known as the intc0 and intc1 registers, control the operation of all interrupts. by setting various bits within this register using standard bit manipulation instructions, the enable/disable func- tion of the external and timer interrupts can be inde - pendently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the reti instruction. timer/event counter registers this device contains three 16-bit timer/event counters, which have associated register pairs known as tmr0l/ tmr0h, tmr1l/tmr1h and tmr2l/tmr2h. these are the locations where the timers 16-bit value is lo - cated. three associated control registers, known as tmr0c, tmr1c and tmr2c, contain the setup infor - mation for these three timers. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pc, pd, pe and pf. these labeled i/o registers are mapped to specific ad - dresses within the data memory as shown in the data memory table, which are used to transfer the appropri - ate output or input data on that port. with each i/o port there is an associated control register labeled pac, pcc, pdc, pec and pfc, also mapped to specific ad - dresses with the data memory. except pc2 and pc3, the control register specifies which pins of that port are set as inputs and which are set as outputs. pc2 or pc3 are nmos outputs, so the corresponding bits of the con - trol register are not implemented. to setup a pin as an input, the corresponding bit of the control register must be set high and for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipu - lating specific bits of the i/o control registers during nor - mal program operation is a useful feature of these devices. dtmf registers dtmfc, dtmfd, dtrxc, dtrxd the device contains a fully integrated dtmf receiver and generator circuitry for decoding and generation of dtmf signals. the dtmf receiver requires two registers to control its operation, a dtrxc control register to control its overall function and a dtrxd register to store the dtmf decoded signal data. the dtmf generator also requires two registers for its operation, a dtmfc register for its overall control and dtmfd register to store the dig- ital codes that are to be generated as dmtf signals. fsk registers fskc, fsks, fskd, peric the device contains a fully integrated fsk decoder. the fsk interrupt function is controlled by two registers, peric and fskc. the fsks register is for the designer to check the interrupt status and a fskd resister to store the decoded fsk cooked data. mode register mode, mode_1 the device supports two system clocks and four opera - tion modes. the system clock can be ether a low frequency 32768hz oscillator or a high frequency hclk oscillator. the operation modes can be either normal, green, sleep or idle. these are all selected using soft - ware. mode_1 register supports four high frequency clocks (hclk) for the mcu which are 3.58mhz, 7.16mhz, 10.74mhz and 14.32 mhz. mfic register mfic0 pc0, pc5 and pc7 can be used to trigger an extra inter - rupt. they are enabled or disabled individually by bit0~bit2 of mfic0. when a multi-function interrupt oc - HT95R54/ht95r55 rev. 1.00 19 march 3, 2010 curs, the programmer should check bit4~bit6 of mfic0 to determine the cause of the interrupt. mfic1 register mfic1 the spi/i 2 c interrupt, external peripheral interrupt, timer 2 interrupt are three additional multi-function inter - rupts. they are enabled or disabled individually by bit0~2 of mfic1. when a multi-function interrupt occurs, the programmer should check bit4~bit6 of mfic1 to de - termine the cause of the interrupt. pfd registers pfdc/pfdd the device contains a programmable frequency di - vider function which can generate accurate frequencies based on the system clock. the clock source, enable function and output frequency is controlled using these two registers. rtcc register the device contains a real time clock function other - wise known as the rtc. to control this function a regis - ter known as the rtcc register is provided which provides the overall on/off control and time out flag. dac registers voicec/vol/dal/dah these four registers are for 12-bit dac output data and volume control. low battery detect register lbdc this register is to control the lbd function and to report the low battery status. software com register scomc the pins pd0~pd3 on port d can be used as scom lines to drive an external lcd panel. to implement this function, the scomc register is used to setup the cor - rect bias voltages on these pins. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device pro - vides bidirectional input/output lines labeled with port names pa, pc, pd, pe and pf. these i/o ports are mapped to the data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output opera - tions. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. unlike the other port lines, pc2 and pc3 are nmos type output-only lines. they have neither pull high op - tion nor a port control bit. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via configuration options and are implemented using a weak pmos transistor. port a wake-up each device has a halt instruction enabling the microcontroller to enter a power down mode and pre - serve power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into entering the power down mode, the device will re - main idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applica- tions that can be woken up via external switches. note that each pin on port a can be selected individually to have this wake-up feature. i/o port control registers each i/o port has its own control register pac, pcc, pdc, pec and pfc, to control the input/output configu- ration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its asso - ciated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos out - put. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. HT95R54/ht95r55 rev. 1.00 20 march 3, 2010 # $ $ # $ ! 4 # ) $ 4 # ! ! $ ! 4 1 8 h 1 ' # # $ l ! 2 l l ! 2 l : " < pa input/output port tmr0/1 pins pin pc4 and pc6 are pin-shared with the external timer input pin tmr0 and tmr1 respectively. for these pin-shared pins to function as timer inputs, the corre - sponding control bits in the timer control register must be correctly set. for applications that do not require an ex - ternal timer input, the pin can be used as a normal i/o pin. note that if used as a normal i/o pin the timer mode con - trol bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. programming considerations within the user program, one of the first things to con - sider is port initialization. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, pac, pcc, pdc, pec and pfc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa, pc, pd, pe and pf, are first programmed. selecting which pins are in - puts and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the en - tire port, modify it to the required new bit values and then rewrite this data back to the output ports. - & % 5 - & % 5 g ! read/write timing : " < l ! 2 l ! 2 ! 4 # ) $ 4 # ! ! $ ! 4 l # # $ l ! 8 d ! - d ! 5 h ! ' 8 h ' 9 8 h 9 ' 8 h ' ? ! 8 d ! 6 d ! ' @ pc (except for pc2 and pc3), pd and pe input/output ports HT95R54/ht95r55 rev. 1.00 21 march 3, 2010 port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the device contains three count-up timers of 16-bit capacity. timer0 and timer1 have three different operating modes, they can be con - figured to operate as a general timer, an external event counter or as a pulse width measurement device. timer2 can be configured to operate in the timer mode only. there are two types of registers related to the timer/event counters. the first are the registers that contains the actual value of the timer/event counter and into which an initial value can be preloaded, and are known as tmr0l/tmr0h, tmr1l/tmr1h and tmr2l/tmr2h. reading these register pairs retrieves the contents of the timer/event counters. the second type of associated register are the timer control regis - ters, which defines the timer options and determines how the timer/event counters are to be used, and have the name tmr0c, tmr1c and tmr2c, timer0 and timer1 can have the timer clock configured to come from the internal clock source or from an external timer pin. timer2 can have the timer clock come from internal system clock only. configuring the timer/event counter input clock source for timer/event counter 0, the internal timer clock source can originate from either the system clock/4 or from an external clock source. for timer/event counter 1, the internal timer clock source can originate from the 32768hz or from an external clock source. an external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer pins tmr0 or tmr1. depending upon the condition of the t0e or t1e bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer registers tmr0l/tmr0h, tmr1l/tmr1h, tmr2l/tmr2h the timer registers are special function register pairs lo - cated in the special purpose data memory and is the place where the 16-bit actual timer value is stored. these register pairs are known as tmr0l/tmr0h, tmr1l/tmr1h and tmr2l/tmr2h. the value in the timer register pair increases by one each time an inter - nal clock pulse is received or an external transition oc - curs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffffh at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. to achieve a maximum full range count of ffffh the preload register must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload register, this data will be immediately written into the actual timer register. however, if the timer/event counter is enabled and counting, any new data written into the preload data register during this period will re- main in the preload register and will only be written into the timer register the next time an overflow occurs. reading from and writing to these registers is carried out in a specific way. it must be noted that when using in - structions to preload data into the low byte register, namely tmr0l, tmr1l or tmr2l, the data will only be placed in a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only carried out when a write to its asso - ciated high byte register, namely tmr0h, tmr1h or tmr2h, is executed. also, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer regis - ters, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer from its associ - ated low byte register. after this has been done, the low byte register can be read in the normal way. note that 4 ! & d ! % l ! 2 l 4 # ! $ pc2, pc3 nmos output port HT95R54/ht95r55 rev. 1.00 22 march 3, 2010 reading the low byte timer register directly will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control registers tmr0c, tmr1c, tmr2c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their control register, which has the name tmr0c/tmr1c/tmr2c. it is the timer control register together with its corresponding timer register pair that control the full operation of each timer/event counter. before the timer/event counter can be used, it is essential that the timer control register is fully pro - grammed with the right data to ensure its correct opera - tion, a process that is normally carried out during program initialisation. to choose which of the three modes the timer/event counter is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair t0m1/t0m0, t1m1/t1m0 and t2m1/t2m0, must be set to the required logic levels. the timer/event counter on/off bit, which is bit 4 of the timer control register, and known as t0on, t1on and t2on, provides the basic on/off control of the timer/event counter. setting the bit high allows the timer/event counter to run, clearing the bit stops it run - ning. if the timer/event counter is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as t0e and t1e. - ( 4 # / g 3 # $ + 3 4 4 # g g ) 4 + 3 4 - ( 4 . 9 / ! # 8 8 9 . 9 / ! # ! 8 ; g b . 5 8 - 8 8 16-bit timer/event counter 0 structure - ( 4 # / g 3 # $ + 3 4 4 # g g ) 4 + 3 4 - ( 4 . 9 / ! # - - 9 . 9 / ! # ! - ; % & ' ( ) * - - - 8 16-bit timer/event counter 1 structure - ( 4 # / g 3 # $ + 3 4 4 # g g ) 4 + 3 4 - ( 4 . 9 / ! # ! & ; g b . 5 & - & 8 16-bit timer2 structure HT95R54/ht95r55 rev. 1.00 23 march 3, 2010 configuring the timer mode in this mode, the timer/event counters can be utilised to measure fixed time intervals, providing an internal in - terrupt signal each time the timer/event counter over - flows. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock, is used as the timer/event counter clock. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and over - flows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, is reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the timer/event counter. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode the external timer pin is used as the timer/event counter clock source, however it is not di - vided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the ac - tive edge select bit, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the coun - ter will increment each time the external timer pin re - ceives a high to low transition. when it is full and overflows, an interrupt signal is generated and the ) * ! ; $ d j 8 j ' 9 / ! # 1 / 9 - c # g 8 c # 8 9 8 ; 8 8 8 - 8 . 9 / ! # ! # 9 - c 8 c $ 8 - 8 8 - - 8 8 8 - 8 - / / # $ # 3 # # # 1 / 9 - c # d $ g 8 c # g d $ ; $ d j 8 j timer/event counter 0 control register = & 9 a $ # 9 m - ! # = % = - event counter mode timing diagram ! # $ # = - = & = ; = ; = - timer mode timing diagram HT95R54/ht95r55 rev. 1.00 24 march 3, 2010 timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, is reset to zero. to ensure that the timer pin is configured to operate as an event counter input pin the timer control register must place the timer/event counter in the event counting mode. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will con - tinue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pin. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width measurement mode bit7 bit6 11 in this mode the internal clock is used as the timer/event counter clock. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is re - ceived on the external timer pin. if the active edge select bit, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin re - turns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the ) + ! ' & ; & 8 & - 8 & - 8 8 - - & 8 8 - 8 - / / / ; $ d j 8 j . 9 / ! # ! # 9 - c 8 c ; $ d j 8 j $ timer2 control register ) , ! ; $ d j 8 j ' 9 / ! # 1 / 9 - c # g 8 c # - 9 - ; - 8 - - 8 . 9 / ! # ! # 9 - c 8 c $ - - 8 8 - - - 8 8 - 8 - / / # $ # 3 # # # 1 / 9 - c # d $ g 8 c # g d $ ; $ d j 8 j timer/event counter 1 control register HT95R54/ht95r55 rev. 1.00 25 march 3, 2010 timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the exter - nal control signal on the external timer pin returns to its original level, whereas in the other two modes the en - able bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter- nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re- load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, is reset to zero. to ensure that the timer pin is configured to operate as a pulse width measurement pin the timer control regis - ter must place the timer/event counter in the pulse width measurement mode. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. in this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not syn - chronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result there may be small differences in measured values requiring pro - grammers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read or if data is writ- ten to the preload registers, the clock is inhibited to avoid errors, however as this may result in a counting er- ror, this should be taken into account by the program- mer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal in- terrupt associated with the timer will remain inactive. the edge select, timer mode control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer register before the timer is switched on; this is because after power-on the initial value of the timer register is unknown. after the timer has been in - itialised the timer can be turned on and off by controlling the enable bit in the timer control register. note that set - ting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. = - = & = % = 5 9 a $ # ; ? 3 9 m 8 @ # $ # ! # # $ # $ / g g - > pulse width measure mode timing diagram HT95R54/ht95r55 rev. 1.00 26 march 3, 2010 when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi - tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the inter - rupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 08h ; timer/event counter 0 interrupt vector jmp tmr0nt ; jump here when timer 0 overflows : org 20h ; main program ;internal timer/event counter interrupt routine tmr0nt: : ; timer/event counter main program placed here : reti : : begin: ;setup timer registers mov a,01fh ; setup preload value timer counts from this value to ffffh mov tmr01,a mov a,09bh mov tmr0h,a mov a,080h ; setup timer control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc0,a set tmrc0.4 ; start timer note mode bits must be previously setup : : HT95R54/ht95r55 rev. 1.00 27 march 3, 2010 serial interface function the device contains a serial interface function, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of commu - nication with external peripheral hardware. having rela - tively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim in - terface function must first be selected using a configura - tion option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using a bit in an internal register. spi interface the spi interface is often used to communicate with ex - ternal peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple commu - nication protocol simplifying the programming require - ments when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the mcu can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, here, as only a single select pin, scs , is provided only one slave device can be connected to the spi bus. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by selecting the sim enable con - figuration option and setting the correct bits in the simctl0/simctl2 register. after the spi configura - tion option has been configured it can also be addi - tionally disabled or enabled using the simen bit in the simctl0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations be - ing implemented by the master. the master also con - trols the clock signal. as the device only contains a single scs pin only one slave device can be utilised. the spi function in this device offers the following fea - tures: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of cer - tain control bits such as csen, simen and scs .in the table i, z represents an input floating condition. there are several configuration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. another two sim configuration options determine if the csen and wcol bits are to be used. configuration option function sim function sim interface or i/o pins spi csen bit enable/disable spi wcol bit enable/disable spi interface configuration options spi registers there are three internal registers which control the over - all operation of the spi interface. these are the simdr data register and two control registers simctl0 and simctl2. note that the simctl1 register is only used by the i 2 c interface. - ) ! - ' . ! 2 ! ! 2 ! spi master/slave connection HT95R54/ht95r55 rev. 1.00 28 march 3, 2010 pin master/salve simen=0 master simen=1 slave simen=1 csen=0 csen=1 csen=0 csen=1 scs =0 csen=1 scs =1 scs zzlzi , zi , z s d ozooooz sdi z i, z i, z i, z i, z z sck z h: ckpol=0 l: ckpol=1 h: ckpol=0 l: ckpol=1 i, z i, z z note: z floating, h output high, l output low, i input, o output level, i,z input floating (no pull-high) spi interface pin status 4 # a . a g 4 # # ! g # $ 9 . ! + ! 9 . ! ! # g b g " 4 . 9 / ! # ! 2 ! ! g # $ ! 9 ; 9 . ! 2 9 ; ! 2 + spi block diagram - ) * ! ; $ d n 8 j . & ! . g - c 8 c $ ! ! 3 . & ! . / ! ! & - 8 8 9 ; d g b . 5 d g b . - ( d g b . ( 5 d % & ' ( ) * d & # $ # . & / & ! ; # 8 8 8 8 - - - - 8 8 - - 8 8 - - ' - 8 & 8 - 8 - 8 - 8 - ! 2 9 ; ! 2 ! - ! 2 ! 8 spi/i 2 c control register simctl0 HT95R54/ht95r55 rev. 1.00 29 march 3, 2010 - ) + ! ' . / $ g - c g 8 c $ g - c 8 c ! $ - c 8 c ! g g - c 4 8 c + 4 ! 9 - c a 8 c a ! - c a 8 c a ; $ d j 8 j 8 ! + ! 9 ; + ! 2 9 ! 2 + spi control register simctl2 - ) , ! ' / 3 g - c 3 8 c 3 & ! # # - c # 8 c # . 3 , # g - c , # 8 c , # 3 3 g - c n 3 8 c 3 . / - c 8 c / & ! # # g - c # 8 c # ! g - c 8 c g g - c g $ 8 c g $ 8 ) < < 1 2 < 1 2 ) 4 4 ) 1 1 ) ! ; ! i 2 c control register simctl1 HT95R54/ht95r55 rev. 1.00 30 march 3, 2010 the simdr register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the microcontroller writes data to the spi bus, the actual data to be transmitted must be placed in the simdr reg - ister. after the data is received from the spi bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the spi bus must be made via the simdr register. bit76543210 label sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxxx there are also two control registers for the spi inter - face, simctl0 and simctl2. note that the simctl2 register also has the name simar which is used by the i 2 c function. the simctl1 register is not used by the spi function, only by the i 2 c function. register simctl0 is used to control the enable/disable function and to set the data transmission clock frequency. al - though not connected with the spi function, the simctl0 register is also used to control the peripheral clock prescaler. register simctl2 is used for other control functions such as lsb/msb selection, write colli- sion flag etc. the following gives further explanation of each simctl1 register bit: simidle the simidle bit is used to select if the spi interface continues running when the device is in the idle mode. setting the bit high allows the spi interface to maintain operation when the device is in the idle mode. clearing the bit to zero disables any spi opera - tions when in the idle mode. this spi/i 2 c idle mode control bit is located at clkmod register bit4. simen the bit is the overall on/off control for the spi inter - face. when the simen bit is cleared to zero to disable the spi interface, the sdi, sdo, sck and scs lines will be in a floating condition and the spi operating current will be reduced to a minimum value. when the bit is high the spi interface is enabled. the sim config - uration option must have first enabled the sim inter - face for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condi - tion and should therefore be first initialised by the ap - plication program. sim0~sim2 these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selec - tion and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the timer. if the spi slave mode is selected then the clock will be supplied by an external master device. sim0 sim1 sim2 spi master/slave clock control and i2c enable 0 0 0 spi master, f sys /4 0 0 1 spi master, f sys /16 0 1 0 spi master, f sys /64 0 1 1 spi master, f sub 1 0 0 spi master timer 2 output/2 1 0 1 spi slave 110i 2 c mode 1 1 1 not used spi control register simctl2 the simctl2 register is also used by the i 2 c interface but has the name simar . trf the trf bit is the transmit/receive complete flag and is set high automatically when an spi data transmis - sion is completed, but must be cleared by the applica - tion program. it can be used to generate an interrupt. wcol the wcol bit is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simdr register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via configu- ration option. csen the csen bit is used as an on/off control for the scs pin. if this bit is low then the scs pin will be disabled and placed into a floating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or en - abled via configuration option. mls this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. ckeg and ckpol these two bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data trans - fer is executed otherwise an erroneous clock edge may be generated. the ckpol bit determines the base condition of the clock line, if the bit is high then the sck line will be low when the clock is inactive. when the ckpol bit is low then the sck line will be high when the clock is inactive. the ckeg bit deter - mines active clock edge type which depends upon the condition of ckpol . HT95R54/ht95r55 rev. 1.00 31 march 3, 2010 ! 2 ? ! 2 + m - @ ! 2 ? ! 2 + m 8 @ ! ! $ # ' . 8 ( . - 6 . & 5 . % % . 5 & . 6 - . ( 8 . ' ? # g ! 2 @ spi slave mode timing (ckeg=0) ! 2 ? ! 2 + m - d ! 2 9 m 8 @ 9 ; d ! 9 ; m - 9 ; m - d ! 9 ; m 8 ? 9 a # ) @ ! 2 ? ! 2 + m 8 d ! 2 9 m 8 @ ! 2 ? ! 2 + m - d ! 2 9 m - @ ! 2 ? ! 2 + m 8 d ! 2 9 m - @ ? ! 2 9 m 8 @ ? ! 2 9 m - @ ! ! $ # ' . 8 ( . - 6 . & 5 . % % . 5 & . 6 - . ( 8 . ' ' . 8 ( . - 6 . & 5 . % % . 5 & . 6 - . ( 8 . ' spi master mode timing ! 2 ? ! 2 + m - @ ! 2 ? ! 2 + m 8 @ ! ! $ # ' . 8 ( . - 6 . & 5 . % % . 5 & . 6 - . ( 8 . ' ? 3 # o m g g ! m - @ ; c / d g 9 ; m - ! 9 ; m 8 d 3 ! / > spi slave mode timing (ckeg=1) HT95R54/ht95r55 rev. 1.00 32 march 3, 2010 9 ; m - ! + m - p ! ! + b $ p ? m - p @ ; b g ! g p ; b 9 ; / / 1 1 g g # ! 9 ; + e & c 8 f m 8 8 8 d 8 8 - d 8 - 8 d 8 - - - 8 8 e & c 8 f m - 8 - ; spi transfer control flowchart HT95R54/ht95r55 rev. 1.00 33 march 3, 2010 ckpol ckeg sck clock signal 00 high base level active rising edge 01 high base level active falling edge 10 low base level active falling edge 11 low base level active rising edge spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simdr register, transmission/reception will begin si - multaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simdr register will be transmitted and any data on the sdi pin will be shifted into the simdr regis - ter. the master should output an scs signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled be - fore/after an scs signal is received. the spi will continue to function even after a halt in- struction has been executed. i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data trans- fer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this rea - son it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and re - ceived on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. a configuration option exists to allow a clock other than the system clock to drive the i 2 c interface. another configuration option determines the debounce time of the i 2 c inter - face. this uses the internal clock to in effect add a debounce time to the external clock to reduce the pos- sibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. sim function sim function sim interface or seg pins i 2 c clock i 2 c runs without internal clock disable/enable i 2 c debounce no debounce, 1 system clock; 2 system clocks i 2 c interface configuration options i 2 c registers there are three control registers associated with the i 2 c bus, simctl0, simctl1 and simar and one data register, simdr . the simdr register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simdr register. after the data is received from the i 2 c bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the i 2 c bus must be made via the simdr register. note that the simar register also has the name simctl2 which is used by the spi function. bits simidle , simen and bits sim0~sim2 in register simctl0 are used by the i 2 c interface. the simctl0 register is shown in the above spi section. 1 g / . g 1 3 g / g 1 3 g / g HT95R54/ht95r55 rev. 1.00 34 march 3, 2010 simidle the simidle bit is used to select if the i 2 c interface continues running when the device is in the idle mode. setting the bit high allows the i 2 c interface to maintain operation when the device is in the idle mode. clearing the bit to zero disables any i 2 cop - erations when in the idle mode. this spi/i 2 c idle mode control bit is located at clkmod register bit4. simen the simen bit is the overall on/off control for the i 2 c interface. when the simen bit is cleared to zero to disable the i 2 c interface, the sda and scl lines will be in a floating condition and the i 2 c operating cur- rent will be reduced to a minimum value. in this con- dition the pins can be used as seg functions. when the bit is high the i 2 c interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the i 2 c control registers will be in an unknown condition and should therefore be first initialised by the application program. sim0~sim2 these bits setup the overall operating mode of the sim function. to select the i 2 c function, bits sim2~ sim0 should be set to the value 110. rxak the rxak flag is the receive acknowledge flag. when the rxak bit has been reset to zero it means that a correct acknowledge signal has been re - ceived at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxak bit to determine if the receiver wishes to receive the next byte. the trans - mitter will therefore continue sending out data until the rxak bit is set high. when this occurs, the transmitter will release the sda line to allow the master to send a stop signal to release the bus. srw the srw bit is the slave read/write bit. this bit de - termines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address match, that is when the haas bit is set high, the device will check the srw bit to determine whether it should be in transmit mode or receive mode. if the srw bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. when the srw bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. txak the txak flag is the transmit acknowledge flag. af- ter the receipt of 8-bits of data, this bit will be trans- mitted to the bus on the 9th clock. to continue receiving more data, this bit has to be reset to zero before further data is received. htx the htx flag is the transmit/receive mode bit. this flag should be set high to set the transmit mode and low for the receive mode. hbb the hbb flag is the i 2 c busy flag. this flag will be high when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be reset to zero when the bus is free which will occur when a stop signal is detected. hass the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the ad - dresses match then this bit will be high, if there is no match then the flag will be low. hcf the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon com - pletion of an 8-bit data transfer the flag will go high and an interrupt will be generated. & ! ? @ / 1 ? 1 @ g ! " < 1 ) 1 1 4 & ! # $ + 4 # 4 . / ! " ! $ $ 4 # 1 ! $ 9 . 1 3 . 3 / 4 ) 4 4 4 ) < 4 ! + 1 ) ! 4 i 2 c block diagram HT95R54/ht95r55 rev. 1.00 35 march 3, 2010 i 2 c control register simar the simar register is also used by the spi interface but has the name simctl2. the simar register is the location where the 7-bit slave address of the microcontroller is stored. bits 1~7 of the simar register define the microcontroller slave address. bit 0 is not defined. when a master device, which is con - nected to the i 2 c bus, sends out an address, which matches the slave address in the simar register, the microcontroller slave device will be selected. note that the simar register is the same register as simctl2 which is used by the spi interface. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmis - sion, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all de - vices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haas bit in the simctl1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service rou - tine, the microcontroller slave device must first check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the microcontroller to de- termine whether to go into transmit or receive mode. be- fore any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simar. step 2 set the simen bit in the simctl0 register to 1 to en - able the i 2 c bus. step 3 set the ehi bit of the interrupt control register to enable the i 2 c bus interrupt. start signal the start signal can only be generated by the mas - ter device connected to the i 2 c bus and not by the microcontroller , which is only a slave device. this start signal will be detected by all devices con - nected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to deter- mine which slave device the master wishes to com- municate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, de - fines the read/write status and will be saved to the srw bit of the simctl1 register. the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the in - terrupt source has come from a matching slave ad - dress or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simdr register, or in the receive mode where it must implement a dummy read from the simdr regis - ter to release the scl line. / 1 1 9 e & c 8 f m - - 8 9 9 ; & ! 4 # # $ m p 9 9 9 ) g # $ ! + 9 ) ) 3 & ! 4 # i 2 c bus initialisation flow chart - ) ! ' ; $ d j 8 j & ! / / 8 1 6 1 5 1 ( 1 8 1 % 1 & 1 - i 2 c slave address register simar HT95R54/ht95r55 rev. 1.00 36 march 3, 2010 ) 1 1 m - p ) < m - p m - p b ; b ; < 1 2 m - p b ; ; g 9 b # g 9 9 9 ) < # ! + ) < ! + < 1 2 9 9 ! + ) < ! + < 1 2 i 2 c bus isr flow chart - 8 - 8 8 - 88 - 8 8 - 8 - 8 - - m ? - @ 1 m / 1 ? ' @ m ? - @ m / / 3 ? - @ m ? @ 1 m 1 ! 2 ? < 1 2 g d < 1 2 g / - @ m $ ? - @ ! + 1 1 ! 2 1 ! 2 $ ! + 1 / 1 1 1 1 1 1 1 i 2 c communication timing diagram HT95R54/ht95r55 rev. 1.00 37 march 3, 2010 srw bit the srw bit in the simctl1 register defines whether the microcontroller slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. if the srw bit is set to 1 then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw bit is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the microcontroller slave device must be setup to read data from the i 2 c bus as a receiver. acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas bit is high, the addresses have matched and the microcontroller slave device must check the srw bit to determine if it is to be a transmitter or a receiver. if the srw bit is high, the microcontroller slave device should be setup to be a transmitter so the htx bit in the simctl1 register should be set to 1 if the srw bit is low then the microcontroller slave device should be setup as a receiver and the htx bit in the simctl1 register should be set to 0 . data byte the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge sig - nal, level 0 , before it can receive the next data byte. if the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the sda line and the master will send out a stop signal to re - lease control of the i 2 c bus. the corresponding data will be stored in the simdr register. if setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the simdr regis - ter. if setup as a receiver, the microcontroller slave de - vice must read the transmitted data from the simdr register. receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the microcontroller slave device, which is setup as a transmitter will check the rxak bit in the simctl1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pclk , is shared with an i/o pin, the required pin function is chosen via pcken in the simctl0 register. the peripheral clock function is controlled using the simctl0 register. the clock source for the peripheral clock output can origi - nate from either the timer 2 divided by two or a divided ratio of the internal f sys clock. the pcken bit in the simctl0 register is the overall on/off control, setting the bit high enables the peripheral clock, clearing it dis - ables it. the required division ratio of the system clock is selected using the pckpsc0 and pckpsc1 bits in the same register. if the system enters the sleep mode this will disable the peripheral clock output. ! + 1 3 $ data timing diagram g b & & ! + 2 9 5 ! + 2 9 5 - d 5 d ! 2 9 ; ! 2 ! 8 ! 2 ! - $ peripheral clock block diagram HT95R54/ht95r55 rev. 1.00 38 march 3, 2010 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the external interrupt is controlled by the action of the external int , pint pins, while the internal inter- rupt are controlled by timer/event counter 0 or 1 over- flow, a real time clock overflow, a dtmf reciever valid character reception, an fsk decoder packet data re- ception or a multifunction interrupt. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by two interrupt control registers, intc0 and intc1, located in the data memory. by controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corre - sponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer/event counter 0 or 1 overflow, a real time clock overflow, a reception of a valid dtmf character, a fsk packet data, a rising edge on pc7 or a falling edge on int/pc0/pc5 will all generate an interrupt request by setting their corresponding request flag, if their ap - propriate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the correspond - ing interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruc- tion at this vector will usually be a jmp statement which will take program execution to another section of pro- gram which is known as the interrupt service routine. here is located the code to control the appropriate inter- rupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original pro- gram counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. - ) * ! ; $ d n 8 j . & ! . g - c 8 c ! 2 $ - c # $ # 8 c # $ # . / 3 8 ! # g b g b . 5 g b . & # $ # . & ! 2 ! - 8 8 - - ! 2 ! 8 8 - 8 - 9 ; ' - 8 & ! 2 9 ; ! 2 ! - ! 2 ! 8 peripheral clock output control simctl0 HT95R54/ht95r55 rev. 1.00 39 march 3, 2010 interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source all devices priority reset 1 external interrupt 2 timer 0 interrupt 3 timer 1 interrupt 4 peripheral interrupt 5 real time clock interrupt 6 multi-function interrupt 7 in cases where both external and internal interrupts are enabled and where an external and internal interrupt oc - curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the intc reg - ister can prevent simultaneous occurrences. external interrupt for an external interrupt to occur, the global interrupt en- able bit, emi, and external interrupt enable bit, eei, must first be set. an actual external interrupt will take place when the external interrupt request flag, eif, is set, a situ- ation that will occur when a high to low transition appears on the int line. when the interrupt is enabled, the stack is not full and a high to low transition appears on the exter- nal interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request flag, eif, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i or et1i, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, t0f or t1f, is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow oc - curs, a subroutine call to the timer interrupt vector at lo - cation 08h or 0ch, will take place. when the interrupt is serviced, the timer interrupt request flag, t0f or t1f, will be automatically reset and the emi bit will be automati - cally cleared to disable other interrupts. peripheral interrupt for a peripheral interrupt to occur, the global interrupt enable bit, emi, and the corresponding peripehral inter - rupt enable bit, eperi, must first be set. an actual pe - ripheral interrupt will take place when the peripheral interrupt request flag, perf, is set. this will occur when the dtmf receiver detects a valid character, a ring/line reversal is detected, an fsk carrier detected, an fsk data packet is ready or the fsk raw data exhibit a falling edge. when the interrupt is enabled, the stack is not full and a peripheral interrupt request occurs, a subroutine call to the peripheral interrupt vector at location 10h, will take place. when the interrupt is serviced, the periph - eral interrupt request flag, perf, will be automatically reset and the emi bit will be automatically cleared to dis - able other interrupts. real time clock interrupt for a real time clock interrupt to occur, the global inter - rupt enable bit, emi, and the corresponding real timer clock interrupt enable bit, ertci, must first be set. an actual real time clock interrupt will take place when the real time clock request flag, rtcf, is set, a situation that will occur when the rtc times out which will occur every second. when the interrupt is enabled, the stack is not full and a real time clock interrupt request oc- curs, a subroutine call to the real time clock interrupt vector at location 14h, will take place. when the inter- rupt is serviced, the timer interrupt request flag, rtcf, will be automatically reset and the emi bit will be auto- matically cleared to disable other interrupts. multi-function interrupt for a multi-function interrupt to occur, the global inter- rupt enable bit, emi, and the corresponding multi-func - tion interrupt enable bit, emfi, must first be set. an actual multi-function interrupt will take place when the multi-function interrupt request flag, mff, is set, a situa - tion that will occur when pc0 or pc5 receive a falling edge, pc7 receives a rising edge, an spi/i 2 c interrupt occurs, an external peripheral has a falling edge or a timer2 overflow occurs. when the interrupt is enabled, the stack is not full and a multi-function interrupt request occurs, a subroutine call to the multi-function interrupt vector at location 18h, will take place. when the inter - rupt is serviced, the multi-function interrupt request flag, mff, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. HT95R54/ht95r55 rev. 1.00 40 march 3, 2010 1 # ! a $ g ! 8 d ! 6 ! ' # ! g 3 9 a # $ , # 9 . 9 / ! # 8 # $ , # 8 . 9 / ! # - # $ , # - 9 9 9 8 9 - 9 1 # ! 9 # ) # $ $ # $ , # 9 9 9 ! # $ , # ! 9 ! + 3 # g # # $ , # 9 ! 8 # $ , # ! 8 9 ! 8 ! 6 # $ , # ! 6 9 ! 6 ! ' # $ , # ! ' 9 ! ' . ! # $ , # 9 9 a $ # $ , # 9 9 & # $ , # & 9 & & 2 3 9 # $ , # 2 / # $ , # 9 2 9 2 # $ , # 2 2 + / # $ , # 9 2 ! # $ , # ! 9 ! 2 ; c g 9 2 d 3 2 d 2 ! 2 d # $ > # > interrupt structure programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc register until the corresponding in - terrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. in - terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the con - tents of the register or status register are altered by the interrupt service program, which may corrupt the de - sired control sequence, then the contents should be saved in advance. HT95R54/ht95r55 rev. 1.00 41 march 3, 2010 - / , ! $ # $ 9 - c 8 c ' 8 9 ! 9 9 # g # . # $ 9 - c 8 c ! # $ , # - c / 8 c / 9 ! ! # $ 9 - c 8 c $ # $ , # - c / 8 c / # g # . # $ , # - c / 8 c / ; $ d j 8 j ; $ d j 8 j interrupt control 1 register . 9 / ! # - # $ 9 - c 8 c - / * ! # $ 9 - c 8 c ' 8 9 8 9 9 9 . 9 / ! # 8 # $ 9 - c 8 c . 9 / ! # 8 # $ , # - c / 8 c / 9 8 9 - - 9 a # $ 9 - c 8 c 9 a # $ , # - c / 8 c / . 9 / ! # - # $ , # - c / 8 c / ; $ d j 8 j interrupt control 0 register HT95R54/ht95r55 rev. 1.00 42 march 3, 2010 ) - , ! ' 8 9 9 9 & 9 & . ! # $ - c 8 c ! a $ $ # $ - c 8 c . 9 / ! # & # $ - c 8 c ; $ d j 8 j . ! # $ , # g - c / 8 c / 9 a $ $ # $ , # g - c / 8 c / . 9 / ! # & # $ , # g - c / 8 c / ; $ d j 8 j & & multi-function interrupt control 1 register ) - * ! ' 8 ! 8 # $ ? 9 @ - c 8 c ! 6 # $ ? 9 @ - c 8 c ! ' # $ ? 9 @ - c 8 c ; $ d j 8 j ! 8 # $ ? 9 @ , # - c / 8 c / ! 6 # $ ? 9 @ , # - c / 8 c / ! ' # $ ? 9 @ , # - c / 8 c / ; $ d j 8 j 9 ! 8 ! 8 9 ! 6 9 ! ' ! 6 ! ' multi-function interrupt control 0 register HT95R54/ht95r55 rev. 1.00 43 march 3, 2010 0 - ! ' 8 9 2 / # $ - c 8 c 2 3 g # $ - c 8 c ; $ d j 8 j / , # g - c / 8 c / 2 3 g # $ , # g - c / 8 c / ; $ d j 8 j 9 2 peripheral interrupt control register 1 ! 8 i ; 2 $ 3 3 - c $ 3 3 8 c $ ; $ d j 8 j 2 $ # $ - c 8 c 9 / # $ - c 8 c 9 ! # $ - c 8 c 9 2 $ # - c " ! 8 c " ; $ d j 8 j 2 2 ! 2 ' 2 9 + fsk control register 1 ! 8 9 / # $ g - c 8 c g 3 g 3 2 # $ g - c / 2 j 8 j d j - j 8 c / 2 j 8 j d j - j g 3 g 3 2 3 # $ # n g . > 2 # $ # n g . ; $ d j 8 j 2 $ # $ g - c 2 $ 8 c 2 $ g 3 g 3 g $ > n g . ; $ d j 8 j ! 9 " " ! ; ' 2 fsk status register HT95R54/ht95r55 rev. 1.00 44 march 3, 2010 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. 9 : # 8 > 7 : power-on reset timing chart 9 : : 8 > - - 8 8 basic reset circuit 9 8 > - - 8 8 : : 8 > 8 - - 8 enhanced reset circuit HT95R54/ht95r55 rev. 1.00 45 march 3, 2010 res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. low voltage reset lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be se- lected via configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counters the timer counters will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack # # wdt time-out reset during power down timing chart 9 # 8 > 7 : 8 > 5 : res reset timing chart + : # low voltage reset timing chart # # wdt time-out reset during normal operation timing chart HT95R54/ht95r55 rev. 1.00 46 march 3, 2010 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power-on) res or lvr reset (normal/green) res or lvr reset (sleep/idle) wdt time-out (normal/green) wdt time-out (sleep/idle) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0 0000 0 0000 0 0000 0 0000 u uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 00 xxxx uu uuuu 01 uuuu 1u uuuu 11 uuuu intc0 000 0000 000 0000 000 0000 000 0000 uuu uuuu tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00 01 00 01 00 01 00 01 uu uu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 01 00 01 00 01 00 01 uu uu tmr2h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00 0 00 0 00 0 00 0 uu u fskc 11 11 1 11 11 1 11 11 1 11 11 1 uu uu u fsks x0 1100 x0 1100 x0 1100 x0 1100 xu uuuu fskd 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu lbdc 00 uu uu uu uu peric 00 00 00 00 00 00 00 00 uu uu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 11 1111 11 1111 11 1111 11 uuuu uu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu intc1 000 000 000 000 000 000 000 000 uuu uuu HT95R54/ht95r55 rev. 1.00 47 march 3, 2010 register reset (power-on) res or lvr reset (normal/green) res or lvr reset (sleep/idle) wdt time-out (normal/green) wdt time-out (sleep/idle) dtmfc 0 1 0 1 0 1 0 1 u u dtmfd 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu dtrxc 001 001 001 001 uuu dtrxd 0000 0000 0000 0000 uuuu rtcc 0 0 u u u u u u u u mode 000 00u 00u 00u 00u mode_1 00 00 00 00 00 mfic0 000 000 000 000 000 000 000 000 uuu uuu mfic1 000 000 000 000 000 000 000 000 uuu uuu pfdc 0000 0000 0000 0000 uuuu pfdd 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu simctl0 1110 000 1110 000 1110 000 1110 000 uuuu uuu simctl1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu simdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simar/ simctl2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu scomc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu voicec 0 0 0 0 u vol xxxx uuuu uuuu uuuu uuuu dal xxxx uuuu uuuu uuuu uuuu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented oscillator there are two oscillator circuits within the controller. one is for the system clock which uses an externally connected 32768hz crystal. the other is an internal watchdog oscillator. system crystal/ceramic oscillator the system clock is generated using an external 32768hz crystal or ceramic resonator connected be - tween pins x1 and x2. from this clock source an inter - nal circuit generates a hclk clock source which is also required by the system. this frequency generator circuit requires the addition of externally connected rc com - ponents to pin xc to form a low pass filter for the hclk output frequency stabilisation. watchdog timer oscillator the wdt oscillator is a fully integrated free running rc oscillator with a typical period of 65 s at 5v, requiring no external components. it is selected via configuration op - tion. if selected, when the device enters the power down mode, the system clock will stop running, however the wdt oscillator will continue to run and keep the watch - dog function active. however, as the wdt will consume a certain amount of power when in the power down mode, for low power applications, it may be desirable to disable the wdt oscillator by configuration option. < - < & < ! - 6 % 5 ' crystal/ceramic oscillator HT95R54/ht95r55 rev. 1.00 48 march 3, 2010 operation mode, power-down and wake-up there are four operational modes, known as the idle mode, sleep mode, green mode, and normal mode. the chosen mode is selected using the mode0, mode1 and upen bits in the mode register but also depends upon whether the halt instruction has been executed or not. halt instruction mode1 mode0 upen operation mode 32768hz hclk system clock not executed 1 x 1 normal on on hclk not executed 0 x 0 green on off 32768hz executed 0 0 0 sleep on off stopped executed 0 1 0 idle off off stopped note: x means don t care mode0 will be cleared to 0 automatically after wake-up from idle mode. hclk is frequency from pll, which is 3.58mhz, 7.16mhz, 10.74mhz or 14.32mhz. ) % 2 0 3 , ! ' 8 8 - ) ! + 2 - 8 ; $ d j 8 j 8 8 - - 8 - 8 - % > 6 ) * ? g # @ ' > - ( ) * - 8 > ' 5 ) * - 5 > % & ) * mode_1 register idle mode when the device enters this mode, the normal operating current, will be reduced to an extremely low standby cur - rent level. this occurs because when the device enters the power down mode, both the hclk and 32768hz system oscillators are stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. sleep mode in the sleep mode is similar to the mode, except here the 32768hz oscillator continues running after after the halt instruction has been executed. this feature en - ables the device to continue with instruction execution immediately after wake-up. green mode in the green mode, the 32768hz oscillator is used as the system clock for instruction execution. the following conditions will force the microcontroller enter the green mode: any reset condition from any operational mode any interrupt occurring during the sleep mode or idle mode a port a wake-up from the sleep mode or idle mode ) % 2 0 ! ' 8 ; $ d j 8 j 9 - 9 8 " 9 ; , # # $ / ) ! + 2 - c 8 c % & ' ( ) * 3 ) 1 + # a # - c % & ' ( ) * ? @ 8 c % & ' ( ) * ? $ @ - c ) ! + 2 ! " 8 c % & ' ( ) * ! " mode register HT95R54/ht95r55 rev. 1.00 49 march 3, 2010 normal mode in the normal mode the device uses the hclk gener - ated by the frequency-up conversion circuit as the sys - tem clock for instruction execution. there are four high frequency clock (hclk) for cpu which are 3.58mhz, 7.16mhz, 10.74mhz and 14.32mhz. care must be taken with changing the system clock in normal mode: step 1: clear bit mode1 to 0 step 2: clear upen bit to 0 step 3: set bits of register mode_1 for the frequency of hclk step 4: set bit upen to 1 step 5: execute a 20ms software delay step 6: set bit mode1 to 1 after step 6, the system clock will be changed according to the setting in mode_1. changing the operational mode holtek s telephone controllers support two system clocks and four operational modes. the system clock can be either 32768hz or hclk and the operational mode can be either normal, green, sleep or idle mode. the operation mode is selected using software in the following way: normal mode to green mode: clear bit mode1 to 0 , which will change the opera- tional mode to the green mode. the upen bit status is not changed. however, the upen bit can be cleared by software. normal mode or green mode to sleep mode: step 1: clear bit mode0 to 0 step 2: clear bit mode1 to 0 step 3: clear bit upen to 0 step 4: execute the halt instruction after step 4, the operational mode will be changed to the sleep mode. normal mode or green mode to idle mode: step 1: set bit mode0 to 1 step 2: clear bit mode1 to 0 step 3: clear bit upen to 0 step 4: execute the halt instruction after step 4, the operational mode will be changed to the idle mode. green mode to normal mode: step 1: set bit upen to 1 step 2: execute a 20ms software delay step 3: set bit mode1 to 1 after step 3, the operational mode will be changed to the normal mode. sleep mode or idle mode to green mode: method 1: the occurrence of any reset condition method 2: any active interrupt method 3: a port a wake-up note that a timer/event counter 0/1 and rtc interrupt will not be generated when in the idle mode as the 32768hz crystal oscillator is stopped. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. care must also be taken with the loads, which are connected to i/os, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up a reset, interrupt or port a wake-up can all wake up the device from the sleep mode or the idle mode. a reset can include a power-on reset, an external reset or a wdt time-out reset. by examining the device status flags, pdf and to, the program can distinguish be- tween the different reset conditions. refer to the reset section for a more detailed description. a port a wake-up and an interrupt can be considered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device using configuration options. when awakened by a port a stimulus, the program will resume execution at the next instruction following the halt instruction. any valid interrupt during the sleep mode or idle mode may have one of two consequences. one is if the re - lated interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. the other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. it is necessary to mention that if an interrupt request flag is set to 1 before entering the sleep mode or idle mode, the wake-up function of the related inter - rupt will be disabled. once a sleep mode or idle mode wake-up event oc - curs, it will take an sst delay time, which is 1024 sys - tem clock periods, to resume to the green mode. this means that a dummy period is inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed im - mediately after the dummy period has finished. to minimise power consumption, all the i/o pins should be carefully managed before entering the sleep mode or idle mode. HT95R54/ht95r55 rev. 1.00 50 march 3, 2010 the sleep mode or idle mode is initialised by a halt instruction and results in the following. the system clock will be turned off. the wdt function will be disabled if the wdt clock source is the instruction clock. the wdt function will be disabled if the wdt clock source is the 32768hz oscillator in the idle mode. the wdt will still function if the wdt clock source is the wdt internal oscillator. if the wdt function is still enabled, the wdt counter and wdt prescaler will be cleared and resume counting. the contents of the on chip data memory and registers remain unchanged. all the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared by hardware. scom function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~ scom3, are pin shared with certain pin on the pd0~ pd3 port. the lcd signals (com and seg) are gener - ated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pd0~pd3 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this en- ables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1 / 2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port d pins are used for lcd driving. note that the port control register does not need to first setup the pins as outputs to enable the lcd driver operation. scomen comnen pin function o/p level 0 x i/o 0or1 1 0 i/o 0or1 1 1 scomn v dd /2 output control lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is imple- mented using the isel1 and isel0 bits in the scomc register. % ) ! ' 8 ! 8 9 ; 8 ! 8 8 c - c ! % - ! - 8 c - c ! % & ! & 8 c - c ! % % ! % 8 c - c ! % ! # . g g 8 c - c ! ! 9 ; g ! 9 ; m - ! $ # ? : m 6 : @ 9 + - d 9 + 8 c 8 8 c & 6 1 8 - c 6 8 1 - 8 c - 8 8 1 - - c & 8 8 1 / 4 - c " $ $ # ; 8 c ! / # * g $ ! - 9 ; ! & 9 ; ! % 9 ; ! 9 ; 9 + 8 9 + - scomc register : ! 8 h ! % ! 9 ; ! 9 ; : . & ! $ # lcd com bias HT95R54/ht95r55 rev. 1.00 51 march 3, 2010 watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by one of three sources selected by a configuration option. these can be its own self-contained dedicated internal wdt oscillator, exter - nal 32768hz or the instruction clock which is the system clock divided by 4. note that if the wdt configuration option has been disabled, then any instruction relating to its operation will result in no operation. a configuration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator or 32768hz oscillator is therefore the recommended choice. under normal mode and green mode operation, a wdt time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep mode or idle mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, succes - sive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly, after the clr wdt2 instruc - tion has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. & 4 2 ! ' 8 $ & 8 8 8 8 - - - - - 8 8 - - 8 8 - - 8 8 - 8 - 8 - 8 - - c - - c & - c 5 - c - c - ( - c % & - c ( 5 - c - & ; # - 8 watchdog timer register ! # ! g # $ ! $ ! g # $ ! + - ! + & ! + 7 ! # g b . 5 - & # ! # g % & ' ( ) * ' ! # - " < # 8 h & watchdog timer HT95R54/ht95r55 rev. 1.00 52 march 3, 2010 dtmf generator the device includes a fully integrated dtmf, dual-tone multiple-frequency, generator function. this functional block can generate the necessary16 dual tones and 8 single tones for dtmf signal generation. the signal will be provided on the dtmf pin of the device. the dtmf generator also includes a power down and a tone on/off function. the clock source for the dtmf generator is the 3.58mhz oscillator. before the dtmf function is used, the device must have been placed into the normal mode. note that the clock source for the dtmf generator is fixed at 3.58mhz and it s not related to which hclk is selected for the device. therefore, the designer doesn t have to switch the hclk to 3.58mhz for this dtmf generator function, if this device is operating under the other hclks, such as 7.16mhz, 10.74mhz and 14.32mhz. dtmf generator control the dtmf generator is controlled by two registers, a control register known as dtmfc and a data register known as dtmfd. the power down mode will terminate all the dtmf generator functions and can be activated by setting the d_pwdn bit in the dtmfc register to 1. these two registers, dtmfc and dtmfd are still accessible even if the dtmf function is in the power down mode. the generation duration time of the dtmf output signal should be deter - mined by the software. the dtmfd register value can be changed as desired, at which point the dtmf pin will output the new dual-tone simultaneously. dtmf generator frequency selection the dtmf pin output is controlled using a combination of the d_pwdn, tone, tr~tc bits. control register bits dtmf pin output status d_pwdn tone tr4~tr1/tc4~tc1 1x x 0 0 0 x 1/2 vdd 0 1 0 1/2 vdd 0 1 any valid value 16 dual tones or 8 signal tones, bias at 1/2 vdd 2 ) ! ' 8 ; 9 3 3 9 - c 8 c i ; ; $ d j 8 j # $ # 9 - c 8 c ; $ d j 8 j dtmf generator control register & 6 8 % ( 7 q 1 4 ! - & % 5 ! + - ! + & ! + % ! + 5 - 5 ' r dtmf dialing matrix 2 ) 2 ' 8 ) # $ ? # @ g , # + 3 # $ ? 3 @ g , # 5 % & - ! 5 ! % ! & ! - dtmf generator data register HT95R54/ht95r55 rev. 1.00 53 march 3, 2010 output frequency (hz) % error specified actual 697 699 +0.29% 770 766 0.52% 852 847 0.59% 941 948 +0.74% 1209 1215 +0.50% 1336 1332 0.30% 1477 1472 0.34% % error does not contain the crystal frequency shift dtmf frequency selection table low group high group dtmf output code tr4 tr3 tr2 tr1 tc4 tc3 tc2 tc1 low high 00010001697 1209 1 00010010697 1336 2 00010100697 1477 3 00011000697 1633 a 00100001770 1209 4 00100010770 1336 5 00100100770 1477 6 00101000770 1633 b 01000001852 1209 7 01000010852 1336 8 01000100852 1477 9 01001000852 1633 c 10000001941 1209 * 10000010941 1336 0 10000100941 1477 # 10001000941 1633 d single tone for testing only 00010000697xx 00100000770xx 01000000852xx 10000000941xx 00000001x 1209 x 00000010x 1336 x 00000100x 1477 x 00001000x 1633 x writing other values to tr4~tr1, tc4~tc1 may generate an unpredictable tone. - . & : ; 9 m - 1 g ; 9 m - ; 9 m 8 g 3 ; 9 m 8 ; 9 m - ; 9 m 8 ; 9 m - ; 9 m 8 i ; m 8 i ; m - dtmf output timing diagrams HT95R54/ht95r55 rev. 1.00 54 march 3, 2010 ; 9 " power-up timing 1 9 . 8 h % : 9 : 1 ! ! 9 1 9 s 1 : = - ! = - : : ! - ! steering timing HT95R54/ht95r55 rev. 1.00 55 march 3, 2010 dtmf receiver the device contains a fully integrated dtmf receiver which will decode the dtmf frequency content of incoming ana - log dtmf signals. an internal operational amplifier is also supplied to adjust the input signal level as shown. there is also a pre-filter function which is a band rejection filter tp reject frequencies between 350hz and 400hz. the low group filter filters the low group frequency signal output, whereas the high group filter filters the high group frequency signal output. each filter output is followed by a zero-crossing detector which includes hysteresis. when the signal amplitude at the output exceeds a specified level, it is transferred into a full swing logic signal. when the input signal is recognized as an effective dtmf tone, a peripheral interrupt will be generated, and the corre - sponding dtmf tone code will be generated. bit no. label r/w function 0 r_pwdn rw dtmf receiver power down enable r_pwdn= 0 the dtmf receiver is in normal mode; r_pwdn= 1 the dtmf receiver is in power down mode after reset, r_pwdn = 1 1 r_inh rw inhibit the detection of tones representing characters a, b, c and d r_inh= 0 detect tones representing characters a, b, c and d r_inh= 1 ignore tones representing characters a, b, c and d after reset, r_inh = 0 2 r_dv rw data valid output flag r_dv= 0 there is no valid dtmf tone received r_dv= 1 there is a valid dtmf tone received 7~3 ro unused bit, read as 0 note: r_dv should be cleared manually if necessary. dtmf receiver status 5 5 - & # : ; : 9 ! - : : : ; : 9 ! & & 6 6 2 7 7 ' - & # : 5 % ! - - : - : & 2 8 ! 8 ' i ; / 3 3 9 - c / $ 3 3 8 c / g $ 1 d 4 d ! - c $ 1 d 4 d ! 8 c $ 1 d 4 d ! / # $ # g - c / / 8 c / / ; $ d j 8 j i ; ) i : dtmf receiver control register 2 8 2 ! ' 8 / # $ # g # 3 i : m - ; $ d j 8 j i % i & i - i 8 dtmf receiver data register HT95R54/ht95r55 rev. 1.00 56 march 3, 2010 dtmf data output table low group (hz) high group (hz) digit d3, d2, d1, d0 697 1209 1 0001 697 1336 2 0010 697 1477 3 0011 770 1209 4 0100 770 1336 5 0101 770 1477 6 0110 852 1209 7 0111 852 1336 8 1000 852 1477 9 1001 941 1336 0 1010 941 1209 * 1011 941 1477 # 1100 697 (note*) 1633 a 1101 770 (note*) 1633 b 1110 842 (note*) 1633 c 1111 941 (note*) 1633 d 0000 (note*): available only when r_inh=0 steering control circuit the steering control circuit is used to measure the effective signal duration and for protecting against a valid signal drop out. this is achieved using an analog delay which is implemented using an external rc time-constant, controlled by the output line est. the timing diagram shows more details. the est pin is normally low and will pull the rt/gt pin low via the external rc network. when a valid tone input is detected, the est pin will go high, which will in turn pull the rt/gt pin high through the rc network. when the voltage on rt/gt rises from 0 to v trt , which is 2.35v for a 5v power supply, the input signal is effective, and the corresponding code will be generated by the code detector. after d0~d3 have been latched, dv will go high. when the voltage on rt/gt falls from v dd to v trt , i.e. when there is no input tone, the dv output will go low, and d0~d3 will maintain their present data until a next valid tone input is produced. by selecting suitable external rc values, the mini - mum acceptable input tone duration, t acc , and the minimum acceptable inter-tone rejection, t ir , can be set. the values of the external rc components, can be chosen using the following formula. t acc =t dp +t gtp ; t ir =t da +t gta ; where t acc : tone duration acceptable time t dp : est output delay time ( l h ) t gtp : tone present time t ir : inter-digit pause rejection time t da : est outptu delay time ( h l ) t gta : tone absent time steering time adjustment circuits HT95R54/ht95r55 rev. 1.00 57 march 3, 2010 ! : . 9 : (a) fundamental circuit: t gtp =r c ln (v dd /(v dd v trt )) t gta =r c ln (v dd /v trt ) - ! : . 9 & - : (b) t gtp HT95R54/ht95r55 rev. 1.00 58 march 3, 2010 fsk decoder the fsk decoder supports four interrupt sources to the peripheral interrupt vector, which are fsk raw data fall - ing edge, ring detect or line reversal detect, fsk carrier detect and fsk packet data. write 1 to the control flag efskdi in peric register, or write 0 to the control flags, rmsk, cmsk and fmsk in fskc register, will enable these interrupts. when any of these interrupts occurs, its interrupt flag (fskdf in peric register; rdetf, cdetf, and fskf in fsks register) will be set to 1 by hardware even if the interrupt is disabled. these interrupts will cause a peripheral interrupt if the periph - eral interrupt is enabled. when the peripheral interrupt occurs, the interrupt request flag perf will be set and a subroutine call to location 10h will occur. returning from the interrupt subroutine, the interrupt flag fskdf, rdetf, cdetf or fskf will not be cleared by hard - ware, the user should clear it by software. if interrupt flag rdetf is not cleared, next ring detect interrupt will be inhibited, other interrupt flags cdetf, fskf, fskdf have the same behavior. the power down mode (f_pwdn=1) will terminate all the fsk decoder func - tion, however, the registers fskc, fsks and fskd are accessible at this power down mode. care must be taken with fsk raw data falling edge inter - rupt. if the efskdi is enabled, then that will disable the rmsk, cmsk and fmsk interrupts. the designer should take care the software design flow to decoder the fsk signals. ring or line reversal detect when no signal is present on the telephone line, rdet will be at gnd and rtime is pulled to vdd by r1. if a line reversal occurs, the rdet1 pin will become high. this causes rtime and internal signal r_det to be pulled low. the c1 and r1 ensure that the r_det signal is low during such a time, so that processor can detect it. when a ring occurs on the line, internal signal r_det is permanently low, indicating the envelope of the ring. if the frequency of the ring must be measured, c1 may be removed, rtime and r_det inverter follow rdet. the flag rdetf will go high when the r_det signal falling edge is detected. this may cause a peripheral interrupt if rmsk is 0 and the peripheral interrupt is enabled (eperi=1). fsk data output the fsk decoder will decode the fsk signal on the tip and ring line and produce two kinds of data formats, the serial data and the 8-bit packet data. it also provides the fsk carrier detection signal. to enable the fsk de - coder, the f_pwdn should be written as 0 . once the fsk carrier signal is detected, the flag cdetf will be set to 1 . this may cause a peripheral interrupt if cmsk is 0 and the peripheral interrupt is enabled. the serial fsk data is present in two formats: raw data and cook data, and could be monitored by the flag dout, doutc, respectively. the flag dout presents the out - put of the decoder when the decoder is at operation mode. this data stream includes the alternate 1 and 0 patterns, the marking and the data. the flag doutc presents the output of the decoder when the decoder is at operation mode. this data stream is like the dout flag but does not include the alternate 1 and 0 patterns. if the fsk data is not detected, the dout and doutc are held high. user can use the fsk raw data falling edge interrupt with dout flag and a timer to implement data decoding by software or by the build-in decoding hardware which is described next. beside the serial data, the decoder also provides fsk packet data. when decoder receives an fsk signal, it will packet 10 bits data to 8 bits data, the first and 10th bits will be discarded. when the 8-bit packet data is valid, it will be stored in the fsk data register fskd, the fsk packet data interrupt flag fskf will be set to 1 . this may cause a peripheral interrupt if fmsk is 0 and the peripheral interrupt is enabled. the fsk packet source could be dout or doutc, selected by fsksel. note that the start bit of the 10 packet bit should be 0 , so the mark signal (one of the fsk data signals) will not be packeted. to detect the carrier signal or decode the serial data or packet 10-bit data to 8-bit data, the operation mode of the controller must be selected in normal mode. when the operation mode is green or sleep, fsk decoder will decode the wrong signal. however, when the operation mode is green or sleep mode and the fsk decoder is at power down mode (f_pwdn=1), the ring and line re - versal detect is still functional. HT95R54/ht95r55 rev. 1.00 59 march 3, 2010 1 ! 8 i ; 2 $ 3 3 - c $ 3 3 8 c $ ; $ d j 8 j 2 $ # $ - c 8 c 9 / # $ - c 8 c 9 ! # $ - c 8 c 9 2 $ # - c " ! 8 c " ; $ d j 8 j 2 2 ! 2 ' 2 9 + fsk control register 1 ! 8 9 / # $ g - c 8 c g 3 g 3 2 # $ g - c / 2 j 8 j d j - j 8 c / 2 j 8 j d j - j g 3 g 3 2 3 # $ # n g . > 2 # $ # n g . ; $ d j 8 j 2 $ # $ g - c 2 $ 8 c 2 $ g 3 g 3 g $ > n g . ; $ d j 8 j ! 9 " " ! ; ' 2 fsk status register 1 2 ! 8 2 $ ' fskd register HT95R54/ht95r55 rev. 1.00 60 march 3, 2010 9 - ; i 9 : ! - 9 - + ; 3 ; 8 - 8 - 8 - > > > - - - - - > > > 2 1 1 r 6 6 > > > > > > 1 1 2 1 1 ! 1 1 3 1 1 % > 6 ) * 9 i ; ! + ! 2 " " ! 2 & 8 > 6 8 > 6 ! g 3 " g 3 ! note: * if the flag fsksel=1, the sync signal data will not be packeted. low battery detection the phone controller provides a circuit that detects the lbin pin voltage level. to enable this detection function, the lben should be written as 1. once this function is enabled, the detection circuit needs 50us to be stable. after that, the user could read the result from lbfg. the low battery detect function will consume power. for power saving, write 0 to lben if the low battery detec - tion function is unnecessary. : 9 + 4 ; + 4 - > - 6 : g : + 4 9 ; - & the battery low threshold is determined by external r1 and r2 resistors. 1.15= vxr2 r1 r2 det + v det = 1.15x(r1+ r2) r2 if we want to detect v det =2.4v then 2.4v= 1.15x(r1 r2) r2 + r1=1.087r2 2 ! 8 + 3 3 8 c - c + 3 g - c + 4 ; $ / - > - 6 : 8 c + 4 ; $ / - > - 6 : ; $ d j 8 j ' + 4 9 ; + 4 lbdc register HT95R54/ht95r55 rev. 1.00 61 march 3, 2010 programmable frequency divider (pfd) generator music a programmable frequency divider function, otherwise known as pfd, is integrated within the microcontroller, providing a means of accurate frequency generation. it is composed of two functional blocks: a prescaler and a general counter. pfd control register the overall pfd function is controlled using the pfdc register. the prescaler is controlled by the register bits, pres0 and pres1. the general counter is programmed by an 8-bit register pfdd. the clock source for the pfd can be se - lected to be either the 3.58mhz/4 or the 32768hz oscillator. to enable the pfd output, the pfden bit should be set to 1. when the pfd is disabled the pfdd register is inhibited to be written to. to modify the pfdd contents, the pfd must be enabled. when the generator is disabled, the pfdd is cleared by hardware. pfd data register bit no. label r/w function 7~0 rw pfd data register pfdd (2fh) register pfd_output_frequency= prescaler_ output 2x(n 1) + , where n = the value of the pfd data # $ # 9 - d 9 8 % & ' ( ) * % > 6 ) * . 5 9 ; # $ # " ! 4 # * * 2 ! 8 ; $ d j 8 j ' # $ # 9 - c 8 c 8 8 c # $ # m g , # # . - 8 - c # $ # m g , # # . & - 8 c # $ # m g , # # . 5 - - c # $ # m g , # # . , # # - c % > 6 ) * . 5 8 c % & ' ( ) * 9 - 9 8 9 ; HT95R54/ht95r55 rev. 1.00 62 march 3, 2010 rtc function when rtc 1000ms time-out occurs, the hardware will set the interrupt request flag rtcf and the rtcto flag to 1 . when the interrupt service routine is serviced, the interrupt request flag (rtcf) will be cleared to 0, but the flag rtcto remains in its original values. this bit (rtcto) should be cleared only by software. however, next rtc interrupt will still occur, even though the rtcto flag is not cleared. ! 8 ; $ d j 8 j ' ! # 9 - c 8 c ! # - c ! # # 8 c ! # # ! 9 ; ; $ d j 8 j ! voice output voice control the voice control register controls the dac circuit. if the dac circuit is not enabled, any dah/dal outputs will be invalid. selection the configuration option of pc1/aud for dac audio output first and writing a 1 to the dacen bit will enable the dac circuit, while writing a 0 to the dac bit will disable the dac circuit. audio output and volume control dal, dah, vol, voicec the audio output is 12-bits wide whose highest 8-bits are written into the dah register and whose lowest four bits are written into the highest four bits of the dal regis - ter. bits 0~3 of the dal register are always read as zero. there are 8 levels of volume which are setup using the vol register. only the highest 3-bits of this register are used for volume control, the other bits are not used and read as zero. 9 % - 0 ! 8 ' 1 ! 9 ; 1 ! 9 - c 8 c ; $ d j 8 j voice control register 2 ! ' 8 ; # d j 8 j % & - 8 1 # # $ # digital to analog data low register 2 ! ' 8 - - - 8 7 1 # # $ # ' ( 6 5 digital to analog data high register 9 % ! ' 8 ; # d j 8 j 1 / # : + & : + - : + 8 volume control register configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defined for proper system function, the details of which are shown in the table. name options i/o options wake-up pa port a wake-up selection. defines the activity of wake-up function. all port a have the capability to wake-up the device from a power-down condition. this wake-up function is selected per bit. pull-high pa pull-high pc0~pc1 pull-high pc4~pc7 pull-high pd pull-high pe pull-high pf pull-high option. this option determines whether the pull-high resistance is viable or not. port a pull-high option is selected per bit. port c pull-high option is selected per bit. port d pull-high option is selected per nibble. port e pull-high option is selected per nibble. port f pull-high option is selected per nibble. watchdog options clrwdt this option defines how to clear the wdt by instruction. one clear instruction the clr wdt can clear the wdt. two clear instructions only when both of the clr wdt1 and clr wdt2 have been executed, then wdt can be cleared. wdt watchdog enable/disable wdt clock source wdt clock source selection rc select the wdt osc to be the wdt source. t1 select the instruction clock to be the wdt source. 32khz select the external 32768hz to be the wdt source. pdf options pa3 normal i/o or pfd output pfd source timer0 or timer1 overflow lvr options lvr low voltage reset enable or disable lvr voltage low voltage reset voltage; 2.1v, 3.15v or 4.2v spi options sim enable/disable spi_wcol enable/disable spi_csen enable/disable, used to enable/disable (1/0) software csen function i 2 c option i 2 c debounce time no debounce, 1 system clock debounce, 2 system clock debounce rnic i 2 c running not using internal clock vddio options vddio disable/enable (this pin is used as gpio/pe4 when disabled) vddio pe0 use vdd or vddio (when vddio is disabled, pe0~3 use vdd as power always) vddio pe1 use vdd or vddio vddio pe2 use vdd or vddio vddio pe3 use vdd or vddio HT95R54/ht95r55 rev. 1.00 63 march 3, 2010 name options aud option dac output enable/disable lock options lock all partial lock application circuits single-ended input application circuits HT95R54/ht95r55 rev. 1.00 64 march 3, 2010 ! ! " # ! $ % % & ' ( ) & ' ( ) * + ( % , - % + ( ( . / + " " " 0 1 ) . + / . + $ 2 $ 3 ) $ $ $ $ * + ( , ) % + ( ( . / + ! " # ! $ % & ' # ( & 4 $ ) , % % - " * & / & % 5 $ $ 6 7 / $ $ $ ! $ ! " # 0 ) $ - , 8 9 ' : ( differential input application circuits HT95R54/ht95r55 rev. 1.00 65 march 3, 2010 1 ( ) : : % 8 8 8 > - . . & 6 8 % ( 7 q - 5 ' r . 2 - 2 & 2 % 2 5 2 6 2 ( 2 ' 2 2 7 2 - 8 2 - - 2 - & : : ; : 9 . 9 < - < & % & ' ( ) * < ! % 5 ' - 6 : - 8 9 a # $ - 8 ; ) 2 ) ) ' & " # 5 & # " / ; : 6 > - : - 8 8 8 > - : : - 8 8 8 > - 9 # $ # ! - h ! 5 d ! ( ! 8 ! 6 ! ' 8 > - 9 a . # $ . ) 0 ) % < 2 - - / = % 0 % 2 ) ) ) % / 0 4 0 2 - / + ! ) - ( & a - 8 8 - 8 8 $ 8 > & & 8 8 8 > 8 - 8 > & % % 8 > 8 - 5 ' 8 9 - ; & 8 8 1 " 1 . ! & HT95R54/ht95r55 rev. 1.00 66 march 3, 2010 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. HT95R54/ht95r55 rev. 1.00 67 march 3, 2010 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z HT95R54/ht95r55 rev. 1.00 68 march 3, 2010 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT95R54/ht95r55 rev. 1.00 69 march 3, 2010 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT95R54/ht95r55 rev. 1.00 70 march 3, 2010 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT95R54/ht95r55 rev. 1.00 71 march 3, 2010 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT95R54/ht95r55 rev. 1.00 72 march 3, 2010 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT95R54/ht95r55 rev. 1.00 73 march 3, 2010 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT95R54/ht95r55 rev. 1.00 74 march 3, 2010 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT95R54/ht95r55 rev. 1.00 75 march 3, 2010 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT95R54/ht95r55 rev. 1.00 76 march 3, 2010 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT95R54/ht95r55 rev. 1.00 77 march 3, 2010 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT95R54/ht95r55 rev. 1.00 78 march 3, 2010 package information 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.40 f 0.13 0.23 g 1.35 1.45 h 1.60 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 07 HT95R54/ht95r55 rev. 1.00 79 march 3, 2010 5 5 7 % % % & ( 5 - - ( - ' 1 4 ! 9 ) s 2 HT95R54/ht95r55 rev. 1.00 80 march 3, 2010 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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